AMD Bulldozer Specifications

AMD Bulldozer SpecificationsIf you are not yet jizzing in your pants, then please do so as there has been some new information revealed about AMD’s Bulldozer:

Design Solutions for the Bulldozer 32nm SOI 2-core processor Module in an 8-core CPU

The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metal-gate SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.

Today, AMD will be releasing even more details at ISSCC 2011 as well as tomorrow (February 21-22) and here’s what will be discussed:

Design Solutions for the “Bulldozer” 32nm: Showcasing AMD’s 32nm technology and leading-edge design techniques, this session will discuss the power savings, performance improvements and new competitive features offered up by “Bulldozer”.
Session date and time:
Monday, 2/21, 3:15 p.m.

40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD “Bulldozer”: This session will be used to dive even further into the Bulldozer architecture to understand its out-of-order execution set and how the integer unit performs.
Session date and time:
Monday, 2/21, 3:45 p.m.

An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing: Interested in the technical and design details of “Orochi,” AMD’s upcoming high-end desktop and server processor? This session will discuss the new technologies and power-saving features used in the design.
Session date and time:
Tuesday, 2/22, 2:30 p.m.

A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computer Devices: This session will look at AMD’s first generation Fusion processor, the AMD E-Series APU, formerly codenamed “Zacate,” which combines the power of an x86 CPU and AMD RadeonTM graphics manufactured on a 40nm die. You’ll learn how it was designed and how to optimize performance and energy usage.
Session date and time:
Tuesday, 2/22, 4:15 p.m.

Via: AMD Blog.